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SONY COMPUTER ENTERTAINMNET ANNOUNCES WORLD'S FASTEST 128 BIT CPU "EMOTION ENGINE™" FOR THE NEXT GENERATION PLAYSTATION
Tuesday, March 02, 1999

Contacts:
Molly Smith – 650.655.6044 ()
Samantha Sackin – 213.489.8246 ()

TOKYO, March 2, 1999 Sony Computer Entertainment Inc. is pleased to announce the co-development with Toshiba Corp. of the 128 bit CPU ("EE" or "Emotion Engine ") for use in the next generation of PlayStation . In order to process massive multimedia information at the fastest possible speeds, data bus, cache memory as well as all registers are 128 bits; this is integrated on a single chip LSI together with the state of the art 0.18 micron process technology. The development of a full 128 bit CPU is the first of its kind in the world.

Not only will this new CPU have application for games, but it will be the core media processor for future digital entertainment applications, and has a vastly superior floating point calculation capability compared to the latest personal computers. The new CPU incorporates two 64 bit integer units (IU) with a 128 bit SIMD multimedia command unit, two independent floating point vector calculation units (VU0, VU1), an MPEG 2 decoder circuit (Image Processing Unit/IPU) and high performance DMA controllers onto one silicon chip. The massive combined performance of this CPU permits complicated physical calculation, NURBS curved surface generation and 3D geometric transformations, which are difficult to perform in real time with PC CPUs performed at high speeds.

In addition, by processing the data at 128 bits on one chip, it is possible to process and transfer massive volumes of multimedia data. CPUs on conventional PCs have a basic data structure of 64 bits, with only 32 bits on recent game consoles. The main memory supporting the high speed CPU uses the Direct Rambus DRAM in two channels to achieve a 3.2 GB/second bus bandwidth. This equates to four times the performance of the latest PCs that are built on the PC-100 architecture.

By incorporating the MPEG 2 decoder circuitry on one chip, it is now possible to simultaneously process high-resolution 3D graphics data at the same time as high quality DVD images. The combination of the two allows the introduction of a new approach to digital entertainment and real-time graphics and audio processing.

With a floating point calculation performance of 6.2 GFLOPS/second, the overall calculation performance of this new CPU matches that of a super computer. When this is applied to the processing of geometric and perspective transformations normally used in the calculation of 3D computer graphics (3DCG), the peak calculation performance reaches 66 million polygons per second. This performance is comparable with that of high-end graphics workstations (GWS) used in motion picture production.

Sony Computer Entertainment America, a division of Sony Computer Entertainment America Inc., markets the PlayStation game console for distribution in North America, develops and publishes software for the PlayStation game console, and manages the U.S. third party licensing program. Based in Foster City, Calif., Sony Computer Entertainment America Inc. is a wholly-owned subsidiary of Sony Computer Entertainment Inc.

Rambus is a registered trademark of Rambus Inc.

Emotion Engine Features and General Specifications
CPU Core: 128 bit RISC (MIPS IV-subset)
Clock Frequency: 300 MHz
Integer Unit: 64 bit (2-way Superscalar)
Multimedia extended instructions: 107 instructions at 128 bit width
Integer General Purpose Register: 32 at 128 bit width
TLB: 48 double entries
Instruction Cache: 16 KB (2-way)
Data Cache: 8 KB (2-way)
Scratch Pad RAM: 16 KB (Dual port)
Main Memory: 32 MB (Direct RDRAM 2ch@800MHz)
Memory Bandwidth: 3.2 GB/sec
DMA: 10 channels
Co-processor1: FPU (FMAC x 1, FDIV x 1), Micro Memory (I:4KB D:4KB)
Co-processor2: VU0 (FMAC x 4, FDIV x 1), Micro Memory (I:4KB D:4KB)
Vector Processing Unit VU1 (FMAC x 5, FDIV x 2), Micro Memory (I:16KB D:16KB)
Floating Point Performance: 6.2 GFLOPS
Geometry:
+ Perspective Transformation: 66 million polygons / sec
+ Lighting: 38 million polygons / sec
+ Fog: 36 million polygons / sec
Curved Surface Generation (Bezier): 16 million polygons / sec
Image Processing Unit: MPEG2 Macroblock Layer Decoder
Image Processing Performance: 150 million pixels / sec
Gate Width: 0.18 micron
VDD Voltage: 1.8 V
Power Consumption: 15 watts
Metal Layers: 4
Total Transistors: 10.5 million
Die Size: 240 mm2
Package: 540 pin PBGA



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